module delay(clk,out);
input clk;
output out;
reg [19:0] cnt;
reg temp;
assign out=temp;
always @(posedge clk)
begin
if(cnt<20'b11111111111111111111)
begin
cnt=cnt+1;
temp=1'b0;
end
else
temp=1'b1;
end
endmodule
